1. Field of the Invention
This invention relates to semiconductor processing, particularly to etching of dielectric materials in semiconductor devices, and more particularly to pre-emitter and pre-base etching of silicon dioxide therein.
2. Description of Related Art
U.S. Pat. No. 5,282,925 of Jeng et al. “Device and Method for Accurate Etching and Removal of Thin Film” (commonly assigned) describes a device and a method known as Chemical Oxide Removal (COR) for accurate etching and removal of a thin layer by controlling the surface residence time, thickness and composition of reactant containing film. The COR process employs etching with gaseous reactants comprising HF and NH3. As the gaseous reactants contact the silicon oxide surface, a film of reaction products is formed on the silicon oxide by adsorption or condensation of the reactant gases on the silicon oxide surface at a pressure near the vapor pressure. Generally, the process of Jeng et al. etches silicon oxide from a wafer by admitting reactant vapor to a chamber which forms a film on a wafer. Etching is adjusted by controlling the film as well as chamber temperature. After etching is completed, the resulting residue can be removed by thermal desorption.
U.S. Pat. No. 5,980,770 of Ramachandran et al. for “Removal of Post-RIE Polymer on Al/Cu Metal Line” (commonly assigned) describes a COR application which removes RIE sidewall films from an aluminum line employing an etching agent comprising a gaseous or plasma mixture of HF as an etching gas and NH3 as an acid neutralizing gas to remove post-RIE polymer rails on an Al/Cu metal line by chemically modifying the polymer rails into a water soluble form. It is best reacted with COR in the RIE cluster before removal into the atmosphere so that the RIE sidewall does not cause corrosion of the aluminum line. The tool cluster is a conventional RIE cluster with a unique combination of process modules.
U.S. Pat. No. 6,335,261 of Natzle, et al. for “Directional CVD Process with Optimized Etchback” describes a COR process producing a solid reaction product “believed to be ammonium hexafluorosilicate ((NH4)2 SiF6)” which has a specific volume approximately three times that of the original silicon dioxide producing a reaction at an overhang that causes a gap to be closed, so that after the gap is closed no further etching of an oxide underlying that closed gap occurs. However, etching continues at the oxide layer on the upper surface of the substrate. The solid product slows the reaction by impeding diffusion of the NH3/HF reactants through the product to the underlying oxide, and as a result the etching process reaches a self-limiting point where the solid reaction product becomes too thick to permit further etching of the underlying oxide.
U.S. Pat. No. 6,194,286 B1 of Torek for “Method of Etching Thermally Grown Oxide Substantially Selectively Relative to Deposited Oxide” describes processing deposited silicon oxide (e.g. silicon oxide formed by PECVD) and outwardly exposed grown silicon oxide materials (which may be thermally grown). The outwardly exposed silicon dioxide layer is vapor etched substantially selectively to the deposited silicon dioxide layer using an etch chemistry comprising a substantially anhydrous HF (no greater than 10% water by volume) and an organic primer (e.g alcohols and ketones).
U.S. Pat. No. 5,223,443 of Chinn et al. for “Method for Determining Wafer Cleanliness” describes a method for determining the cleanliness of a semiconductor wafer comprising the steps of depositing a thin tetraethylorthosilicate (TEOS) glass film over the entire surface of a wafer and then exposing the wafer to a solution of KOH that attacks the polysilicon, but which is selective to and does not etch the TEOS glass film for the purpose of exposing pin holes during visual inspection.
In the past, integrated tools which include multi-processing, multichamber systems which transport single wafers between a series of interconnected process chambers have been provided as exemplified by U.S. Pat. Nos. 5,076,205; 4,917,556; 5,024,570; and Japanese JP1 0036970A which are discussed below.
U.S. Pat. No. 5,076,205 of Vowles et al. for “Modular Vapor Process System” shows a multichamber, multi-processing, system in which individual processing chambers are mobile to permit exchange thereof readily without requiring complete evacuation of the system. The processing capability of the system is extended by using a wafer buffer storage cassette/elevator system. The system is expanded to include a number of processing chambers permitting wafer input and output access at intermediate points.
U.S. Pat. No. 4,917,556 of Stark et al. for “Modular Wafer Transport and Processing System” describes a wafer processing machine including multiple loadlocks for loading whole cassettes into the vacuum environment. However, the wafers are transported individually. Wafer handling modules containing robot arms from a spine of the machine through which wafers are passed. Various processing modules are attached to the sides of the wafer handling modules.
U.S. Pat. No. 5,024,570 of Kiriseko et al. for “Continuous Semiconductor Substrate Processing System” describes a wafer processing system which includes a stocker coupled to the conveying mechanism to hold semiconductor wafers temporarily during the processing, but it does not transport the wafers in a vacuum. It also includes a wafer storage section for storing semiconductor wafers; a transfer mechanism for transferring semiconductor wafers between storage section and conveying mechanism; a wafer discrimination section for discriminating the semiconductor wafers; and a carrier feed-in-feed-out section capable of feeding in and feeding out semiconductor wafers.
JP10036970A of Kiyoshi for “Thin Film Vapor Growth Apparatus” provides a transfer chamber for carrying a wafer from an adjacent vacuum chamber onto a reactor (growth chamber) for growing a thin film on the wafer in the vacuum chamber. The apparatus provides for linear transport of a single wafer without even unchucking the wafer.
A number of defects are associated with stripping of silicon oxide from the surface of a workpiece such as a doped silicon semiconductor substrate with an aqueous HF solution, prior to deposition of base and emitter regions in bipolar devices, in BiCMOS integration schemes and in strained CMOS devices (for example, devices described in commonly assigned U.S. Pat. No. 6,429,061 of Rim for “Method to Fabricate a Strained Si CMOS Structure Using Selective Epitaxial Deposition of Si after Device Isolation Formation.” Such defects may be caused directly by damage from exposure to the aqueous solution or indirectly by the effects from the inherent delay resulting from the changes which occur in the exposed surface of the workpiece. For example, the surface may be exposed to harmful gases in an ambient atmosphere during the time between aqueous HF treatment and a subsequent vacuum deposition process.
It is well known that an aqueous HF solution can leave a partially passivated surface on a silicon, semiconductor substrate, thus enabling a non-integrated oxide strip, but the remaining delay is a manufacturing problem, especially for the case of etching before forming the base of a transistor, i.e. a “pre-base etch”. Since aqueous etches are generally batch processes, the delay is particularly severe when deposition involves a subsequent single wafer process, or if a single wafer strip precedes a batch deposition. Such a wet single wafer strip is described in U.S. Pat. No. 6,162,739 of Sumnitsch et al. assigned to SEZ Semiconductor-Equipment Zubehor fur die Halbleiterfertigung AG for a “Process for wet etching of semiconductor wafers.” The process of Sumnitsch et al. '739 includes entirely removing a silicon dioxide layer from a top side and selectively removing the silicon dioxide layer from the opposite side in a defined area which extends to the inside from the peripheral edge of the semiconductor wafer, using an etching medium which includes hydrofluoric acid or a combination of hydrofluoric acid and ammonium fluoride and at least one carboxylic acid.
If a single wafer strip such as described in the '739 patent precedes a batch deposition, the delay is lengthened by the processing mismatch between a batch and single wafer operation.
A summary of some problems associated with conventional aqueous etch processing is as follows:
(A) Exposed silicon oxide located spaced away from the base or emitter regions is attacked, creating shorts between the emitter and the base or producing detrimental topography in Shallow Trench Isolation (STI) and elsewhere, so that it is difficult to provide later silicidation of overlying silicon.
(B) Isolation features between the base and the emitter can be undercut.
(C) Defects and crevices in exposed silicon, which later becomes the polysilicon gate for an accompanying CMOS device, can be penetrated by the aqueous etching solution, thereby attacking the underlying gate oxide layer.
(D) Residual silicon oxide from regrowth at the base/collector interface can produce defects during base epitaxy leading to leakage between emitter and collector; residual silicon oxide from regrowth at the base/emitter interface can contribute to higher resistance between the base and the emitter. If partial silicon oxide regrowth is followed by additional wet cleans able to remove the silicon oxide, then silicon reacted during oxide regrowth will be consumed, contributing to defects.
Further details regarding these problems are given below.
(A) Attack of Exposed Silicon Oxides (Example: Emitter Pre-Etch)
During fabrication of the new generation of SiGe BiCMOS, a critical step involves the achievement of isolation between the emitter polysilicon and the extrinsic polysilicon by means of insulators such as TetraEthylOrthoSilicate (TEOS) silicon oxide, hereinafter referred to as TEOS. The starting thickness of the TEOS is within a certain range between about 500 Å and about 1000 Å, as defined by the previous CMP processes.
There is also a stringent thermal requirement after deposition of the base, namely that in order to avoid severe dopant diffusion, any high temperature annealing for the purpose of hardening the TEOS is strictly prohibited.
Before the deposition of the emitter polysilicon, it is required that the thin HIPOX protection film (about 100 Å) on top of the base layer must be removed. There are several problems associated with the exposure of the isolation TEOS and the protection of the HIPOX (High Pressure OXide) layer at the same time during the removal of the HIPOX layer.
A HIPOX layer is kind of silicon oxide layer which is the product of a high pressure oxidation process. The HIPOX process can employ high pressure steam, high pressure oxygen, or a combination thereof to produce a silicon oxide layer. See U.S. Pat. No. 5,128,271 of Bronner et al., which indicates that the essential process sequence of the HIPOX process is described in “Low Temperature, High Pressure Steam Oxidation of Silicon,” by L. E. Katz and B. F. Howells, Jr. in J. Electrochem. Soc., Vol. 126, p. 1822 (1979), which is hereby incorporated by reference. In an exemplary HIPOX process, the base is formed on a bare N-epi/N+ subcollector/P-substrate with an annealed reach-through implant. A 100 Å etch stop oxide (ESOX) is grown by HIPOX (e.g., in 10 atmospheres of steam at 700° C.), followed by formation of a P+ in-situ doped polysilicon extrinsic base and a TEOS layer. A hole is etched to the ESOX; a sidewall is then formed on the ESOX. The ESOX is then stripped with aqueous HF, and emitter polysilicon is deposited, doped and patterned. Emitter anneal (e.g., 850° C. for 20 min.), contact, and metallization steps are then performed.
Two consequences of the conventional HIPOX process are as follows:
(1) The TEOS layer covering the extrinsic polysilicon base will be completely removed, when the thin HIPOX layer for the base protection is stripped by HF during the process of forming the emitter opening. This is due to the much higher etch rate of the TEOS compared to the silicon oxide; wet HF etch removes TEOS about 10 times faster than the HIPOX.
(2) Even with a HIPOX oxidation of the extrinsic polysilicon to achieve a soft etch stop for the DHF wet strip, the thick TEOS will be mostly removed causing not only potential leakage in case there are defects in the HIPOX, but also severe increase in the parasitic capacitance. So, from the device performance point of view, maintaining a thick TEOS is highly desirable.
Furthermore, as noted above, undesirable topography is produced on STI (Shallow Trench Isolation) which results in part from the aqueous HF etch associated with a pre-base strip.
(B) Undercutting of Emitter/Base Sidewall Isolation
FIGS. 1A and 1B illustrate the problem of undercutting of emitter/base sidewall isolation nitride in a bipolar device BP. FIG. 1A shows bipolar device BP formed of a silicon substrate SI covered with a HIPOX layer HX, upon which a polysilicon layer PS and a TEOS layer TS are formed with a window W therethrough exposing the central portion of the HIPOX layer HX. Silicon nitride sidewall spacers SW have been formed on the sidewalls of the layers PS and TS. An aqueous solution of HF undercuts HIPOX layers in a HIPOX strip which can cause problems with the bipolar portion of a device.
FIG. 1B shows the device BP of FIG. 1A after an aqueous solution of HF has been used to strip the HIPOX layer HX at the base of the window W. One problem is that the TEOS has been etched away, i.e. completely removed as an unwanted side effect of removing the exposed portions of the HIPOX layer HX. Furthermore, an undercut UC has been formed below the sidewall spacers SW and possibly, as shown, extending under the polysilicon layer PS which is now cantilevered. The undercut UC is very problematic for process control often resulting in defect, leakage, or unwanted topography.
There is a need for an etching process which does not have the adverse side effect of undercutting below the sidewall nitride, i.e. which limits undercutting of the HIPOX layer and the like.
(C) Penetration of Defects in Polysilicon Gate Layer of CMOS Devices
HF penetrates polysilicon during a HIPOX strip which can cause problems with the CMOS portion of a device. FIGS. 2A and 2B illustrate the problem for a CMOS device CM which comprises a silicon substrate SI on which a blanket gate oxide layer GX, has been formed, covered by a blanket layer of gate electrode polysilicon GP. In FIG. 2A a CMOS device CM is shown with a polysilicon defect PD in the polysilicon layer GP. FIG. 2B shows the device CM of FIG. 2A after treatment with an aqueous solution of HF which has penetrated through the defect in the gate polysilicon layer GP to create an oxide defect OD in the gate oxide GX.
Thus an etching process which does not have the adverse side effect of penetrating thin fissures in polysilicon layers and the like is needed.
(D) Residual Silicon Oxide
Regrowth of silicon oxide at the collector/emitter interface following a process of stripping in an aqueous HF solution causes yield loss. The manufacturing process window for atmospheric exposure is as small as 15 minutes between a silicon oxide stripping process and the growth of base epitaxy. Accordingly, there is a need for a silicon oxide etching process which can be integrated into a single tool which can also perform a process for epitaxial growth of a silicon containing layer or polycrystalline growth of a silicon layer.
FIGS. 3A-3E illustrate other aspects of the problem of using a wet chemical etch on a bipolar structure.
FIG. 3A shows a device 10 in an early stage of manufacture. A silicon substrate 12 includes at the bottom a region comprising doped silicon collector 14. A doped silicon base 16 which comprises the intrinsic base region is formed above the silicon collector 14. A thin HIgh Pressure Oxide (HIPOX) layer 18 is formed on the surface of the substrate 12 above the intrinsic base 16. A blanket extrinsic base polysilicon layer 20 (Poly 1) is formed on top of the HIPOX layer 18. A blanket glass film in the form of a TetraEthylOrthoSilicate (TEOS) silicon dioxide layer 22 is formed on the surface of the Poly1 layer 20. The Poly1 layer 20 which is the extrinsic base is electrically connected to the intrinsic base 16 in another region (not shown) and the TEOS layer 22 is provided as electrical insulation between the Poly1 layer 20 and the emitter which is to be added, as shown in FIG. 3E.
FIG. 3B shows the device 10 of FIG. 3A after formation of a window 24 through TEOS layer 22 and polysilicon layer 20 down to the top surface of the HIPOX layer 18 by photolithography and etching, as will be well understood by those skilled in the art.
FIG. 3C shows the device 10 of FIG. 3B after formation of silicon nitride (SiN) spacers 26 from the exposed surface of the HIPOX layer 18 reaching up along the sidewalls of the TEOS layer 22 and the polysilicon layer 20 in the window 24.
FIG. 3D shows the device 10 of FIG. 3C after wet etching with an aqueous solution of HF. In this case, the TEOS layer 22 has been etched away, i.e. completely removed, and the HIPOX layer 18 has been partially etched away below the spacers 26, leaving them less cantilevered than in FIG. 1B, but nevertheless, even this degree of undercut is unacceptable. The removal of the TEOS layer 22 is also undesirable as can be seen with reference to FIG. 3E.
FIG. 3E shows the device 10 of FIG. 3D after an emitter 30 has been formed filling the window 24, covering the spikes of the sidewall spacers 26 which were exposed by the unwanted removal of the TEOS layer 22 and reaching down to short circuit the emitter 30 to the exposed surface of the Poly1 layer 20.
There is a need for an oxide etch process which avoids unwanted attack of exposed silicon oxides, limits undercutting of sidewall isolation, and will not further damage a defective polysilicon layer. Furthermore, there is a need for an oxide etch process which can be integrated with a Si or Si/Ge growth process, so that the wafer need not be exposed to the atmosphere after the etch process.